Hello, I am am trying to get a ring oscillator working in openlane/caravel, but the yosys synth script seems to be optimizing out and replacing them with buf_2 primitives. I have tried a couple things such as adding keeps for the following: -for the wires of the inverters -on the the module instantiating the oscillator -on for the generate block instantiating the sky130_fd_sc_hd__inv_2 primitives for the oscillator. I have also turned off synth_buffering just to test does anyone have any advice for how to make yosys leave these inverters alone?

In verilog: (keep) reg [1023:0] inv_out;

@Arman Avetisyan out of curiosity, do you know how to turn off yosys optimizations completely. We want to test this as well

change the synthesis script to disable the optimizations

Makes sense, I disabled/commented these options in the synth script and found that some logic optimization still happened

i am sure its not the only ones, you need to check with yosys documentation

we've also found that instantiating as a standard cell stops optimisation

Here is what we were trying to do and found it minimizes our ring oscillator regardless of where we end up putting keeps. One thing of note, we are trying to compile this using the caravel version of openlanes flow for one of the chipignite shuttles, are there any additional scripts trying to minimize the logic in this flow/is there any way to perhaps disable abc's advanced optimization?

the only other thing I had to do with this method

semi-related, but did you ever figure out how to do post layout simulation for your ring oscillator and/or STA on a specific path for the oscillator. I remember seeing a post about this when searching.

yes, see the repo I linked above