@Tim Edwards @Mitch Bailey @mehdi have installed the caravel_user_project_analog following the steps mentioned in this repo - https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst#install-caravel. I have a design's gds already with me. How can I integrate that into the user_analog_project_wrapper.gds .

The top level cell you submit must be named

user_analog_project_wrapper.gds

but it may be easier for you to start with the empty wrapper and then rename it. You can drop your GDS into the wrapper any way you want to as long as the wrapper cell exists as the top level and has all the same pins in the same positions. My usual recommendation is just to create one extra layer of hierarchy, so that you have your project's own top level cell inside a cell that wires everything out to the wrapper pins, inside the wrapper cell. But that's just a recommendation.

@Pranav Lulu Can you please clarify this process of integrating user design gds into caravan? What are the steps need to be followed. Need to follow steps given in Caravan repo readme or is it manual integration ?

The actual integration of

gds/user_analog_project_wrapper.gds

into

caravan

is performed by efabless on the platform. It is possible to also do this locally so that you can check the results, but I doubt that most users attempt to do this. If you have a

gds/user_analog_project_wrapper.gds

file and have updated

verilog/rtl/user_defines.v

with your default gpio settings, you can execute the following commands to create an integrated caravan gds.

make gpio_defaults
make truck

This will create

gds/caravan.gds

, but efabless does not use this. Note: the chip id will probably be

00000000

. If you want to change that

export USER_ID="0123ABCD"
make set_user_id

before

make truck

@Mitch Bailey @Arman Avetisyan There are two

gds

folders:

caravel_user_project_analog/caravel/gds

and

caravel_user_project_analog/gds

. Which one to use ? Can you please validate below steps for hardening analog GDS in wrapper. Want to do it manually and not through openlane. 1. Instantiate user design layout inside inside wrapper layout of this gds

caravel_user_project_analog/caravel/gds/user_analog_project_wrapper_empty.gds

2. Copy gds of integrated layout in step 1 at this path

caravel_user_project_analog/caravel/gds/user_analog_project_wrapper.gds

3. Run pre-check using

make precheck

. Will this pre-check harden

user_analog_project_wrapper.gds

into caravel/carvan ?

Try this 1. Copy

caravel_user_project_analog/caravel/gds/user_analog_project_wrapper_empty.gds

to

caravel_user_project_analog/gds/user_analog_project_wrapper.gds

2. Instantiate user design layout inside

caravel_user_project_analog/gds/user_analog_project_wrapper.gds

3. Run pre-check using

make precheck
make run-precheck

This will confirm that your gds is suitable for submission. As I previously mentioned, efabless will harden the

user_analog_project_wrapper.gds

into

caravan

during tapeout. All you need to do is upload your data and pass the platform precheck. I do recommend passing the local precheck first before running the platform precheck.

Thanks @Mitch Bailey, this provides great clarity now. Few more clarifications needed: 1. after instantiating user design layout inside

caravel_user_project_analog/gds/user_analog_project_wrapper.gds

, metal interconnects from user layout pins to wrapper pins need to be done manually? 2. And then metal interconnects from wrapper pins to carvan IO pads will be done automatically by efabless during hardening of

user_analog_project_wrapper.gds

into

caravan

during tapeout? Are these inferences correct ?

exactly!

Thanks very much for confirmation. I was struggling to understand this flow for sometime. It would have been helpful if some kind of brief documentation was available to simplify understanding of these steps. One last clarification, how to upload my pre-checked data on efabless platform.

Glad to help. The

Layout Integration

section here has a brief explanation. This page has a walk-through about uploading to the platform. Let me know if you have problems.

Thanks again 👍

Do you have docker installed?

docker --help

Precheck requires docker to run.

I have installed docker now and run

make precheck

. Getting output as shown in attached screenshot. Don't know what to make of it. Is it correct ? What is expected as output of

make precheck

command ?

I think all the variables are set inside precheck docker, but you probably need to set PDK. Looks like there’s a problem with your docker installation. Try googling

permission denied while trying to connect to the docker daemon socket

make precheck

just sets up the precheck environment.

make run-precheck

does the actual checks.

I was able to run make precheck by adding sudo i.e.

sudo make precheck

. But

sudo make run-precheck

is failing error shown in screenshot. Should I set

export PDK_ROOT=/usr/local/share/pdk

first ?

Running as sudo may start a new shell with new environment variables. I suggest not running as root, but rather fixing the docker installation so that your user can access docker.

I installed docker using some online resource. Can you please share some reference for correct docker installation? I will remove existing docker and re-install it again.

How about this?

Followed the steps in shared link but issue is persisting. Getting authentication failure error. I think my docker installation is missing something or dependencies. Can you share steps how to go with docker installation ?

1. follow the steps to add your user to docker group, to be able to run docker without sudo 2. Delete files created by sudo make precheck otherwise you will get another permission error not related to docker

Looks like your

su -s ${USER}

is failing. Try running

docker run hello-world

in a new shell window.

@Arman Avetisyan @Mitch Bailey I was able to add user to docker group and run

docker run hello-world

succesfully. Following above

make precheck

also ran succesfully (I think so, please confirm seeing output in attached screenshot) But getting following error while running

make run-precheck

PDK Root: /home/vks/git_clone/caravel_user_project_analog/dependencies/pdks doesn't exists, please export the correct path before running make.

make: *** [Makefile:175: check-pdk] Error 1

Please suggest how to resolve this issue.

What is

PDK_ROOT

set to?

I have not set this variable? Should I set it to my PDK path i.e.

/usr/local/share/pdk

Yes.

PDK_ROOT

needs to be set if it is not the default

$PWD/dependencies/pdks

. You should probably set the other environment variables that are not the default value. You can check the default values in the

Makefile

.

OK, the command is running after setting

PDK_ROOT

But I am not able to make sense of results in

precheck.log

file. It is showing error related to LVS. 1. How to debug these results from precheck.log file ? 2. What are the things to look in order to conclude that my design is ready for uploading to efabless shuttle ?

Is there an

lvs/user_analog_project_wrapper/lvs_config.json

file? That’s where you specify everything for LVS. If there’s not, you can copy from here.

@Mitch Bailey Attached is precheck.log file. I have instantiated my design layout inside gds: caravel_user_project_analog/gds/user_analog_project_wrapper.gds 1. What needs to be done with .spice netlist of my local design. Where it should be copied or moved in order to pass LVS ? 2. Any connection needs to be done between pins in my design and wrapper pins in .spice netlist ? 3. What else needs to be rectified as per errors seen in precheck.log file ?

2023-09-16 16:21:24 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 11 non-compliant file(s) with the SPDX Standard.
2023-09-16 16:21:24 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['/home/vks/git_clone/caravel_user_project_analog/gds/.magicrc', '/home/vks/git_clone/caravel_user_project_analog/xschem/example_por_tb.sch', '/home/vks/git_clone/caravel_user_project_analog/xschem/user_analog_project_wrapper.sch', '/home/vks/git_clone/caravel_user_project_analog/xschem/analog_wrapper_tb.sch', '/home/vks/git_clone/caravel_user_project_analog/xschem/.spiceinit', '/home/vks/git_clone/caravel_user_project_analog/xschem/user_analog_project_wrapper.sym', '/home/vks/git_clone/caravel_user_project_analog/xschem/test.data', '/home/vks/git_clone/caravel_user_project_analog/xschem/example_por.sym', '/home/vks/git_clone/caravel_user_project_analog/xschem/xschemrc', '/home/vks/git_clone/caravel_user_project_analog/xschem/example_por.sch', '/home/vks/git_clone/caravel_user_project_analog/xschem/example_por_tb.spice.orig']

These files are missing an open source license header. You can add something like this, but be sure to use the comment syntax appropriate for the file type.

// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      <http://www.apache.org/licenses/LICENSE-2.0>
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

(edit) if your design is closed source, you probably don’t want to do this.

I have attached required files. Meanwhile looking to resolve other issues. Thanks for your help!

Is

xschem/user_analog_project_wrapper.spice

your schematic netlist? It looks like the default analog power on reset schematic netlist. Do you have text and pins on the top level of your gds layout?

I haven't modified anything in

xschem/user_analog_project_wrapper.spice

from its default. Anything to be updated here ?

Do you have any xschem schematics?

Yes, for my opamp design.

Have you integrated that into the top level

user_analog_project_wrapper

?

No, can you please tell how to do this integration. Not able to understand this step.

I’d start with the schematic

xschem/user_analog_project_wrapper.sch

, leave all the pins, but delete the symbols. Then add your top level opamp symbol and connect to the appropriate pins.

@Mitch Bailey as suggested I did modifications in

user_analog_project_wrapper.sch

Then ran make run-precheck. Although LVS_check.log is showing design matching uniquely. But precheck.log shows LVS error. Alongwith that there are few more warnings. Please suggest how to clear them.

What does

$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice

return? It should return an absolute path to

sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

After making above environment setup i.e.

$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice

, 2 errors

('Default', 'GPIO-Defines')

in

precheck.log

are not coming. But

['Consistency', 'LVS']

erros are still there. I am attaching my user_defines.v file. How to setup analog pins in this file? My design uses all analog pins in caravan wrapper i.e.

io_analog[2],[3],[4],[5],[7],[8]

.

Analog pads (

io_analog[10:0]

) have no GPIO setup. If you are using the analog connections to the gpio cells (

gpio_analog[17:0]

,

gpio_noesd[17:0]

), use

GPIO_MODE_MGMT_STD_ANALOG

.

* gpio_analog/noesd [17:7]  <--->  mprj_io[35:25]
     * gpio_analog/noesd [6:0]   <--->  mprj_io[13:7]

I’m hoping the LVS results have changed. Can you resend

LVS_check.log

?

LVS_check.log

is attached. I am sorry but not at all able to understand about setup of

user_defines.v

file. I have no experience of verilog or digital design. Can you please help how can I understand this setup. If possible can you share some sample

user_defines.v

file for analog only design.

no

user_defines.v

settings are needed for

io_analog

pins. You will need to set the

user_defines

for the gpiov2 pads whether you use them or not. I suggest

GPIO_MODE_MGMT_STD_ANALOG

since that will disable the digital I/O.

Please check attached file. Is this right?

@vks: That should be fine.

If you’re worried about leakage current, with

GPIO_MODE_USER_STD_ANALOG

you might want to tie all the unused

io_out

and

io_oeb

to some voltage.