Hi! I am trying to implement a basic inverter in the caravel harness using Openlane and I get the following error message as seen in the attachment. Any suggestions?

Your pin order configuration file states the pins locations. It has two ports in and out. But your verilog is missing these ports. Or vice versa

@Arman Avetisyan It was the pin order config file that was missing the ports. The pin order config file looks like this now. I have commented out the other ports.

out\[36\]
in\[37\]

The verilog file looks like this:

`default_nettype none
module inverter(
`ifdef USE_POWER_PINS
    inout vccd1,	// User area 1 1.8V supply
    inout vssd1,	// User area 1 digital ground
`endif
    input wire in,
    output out);

    assign out = !in;

endmodule

what is the \[36\] mean, i dont see a port with these name in your verilog

@Arman Avetisyan Her is the config.json

share your

pin_order.cfg

as well

Her is the pin_order.cfg file. The Openlane doc recommends not change it from the one found in the user_example_project.

is your verilog has 16bit port size for io_in and io_out?

clearly the pin order config does not match the verilog, which has in and out signals only

I see. So the pin_order.cfg file should look something like this?:

in
out

yes