#1523 Synthesis - ABC: + rewrite failure when running yosys-abc Issue created by ramrajrl Description Yosys Synthesis Fails when running ABC, this error happens on a relatively big arithmetic circuit optimization. Please check this thread from YosysHQ for the details of the issue. YosysHQ/yosys#174 (comment) In Openlane setup -- it is this file -->

scripts/yosys/synth.tcl

Expected Behavior

This error happen on a relatively big arithmetic circuit optimization. I have simplified code and post few examples here. They should lead to equivalent synthesis flow. But in some cases ABC fail and in other it is not. Theoretically it could be ABC issue,

I've been in email contact with Alan Mishchenko, the author of ABC, regarding this problem.

This seems to be a known problem with ABC's

rewrite

command with "highly redundant netlists with deep logic". Alan says this is probably not going to be fixed anytime soon because it means a lot of work in obsolete code. He suggests to simply use the newer

drw

command instead of

rewrite

.

I've now added transforming divide and modulo by a constant power of two to simpler operations in commit 11f7b8a. This avoids generating "highly redundant netlists" for the example you gave in the first place.

Please use the newer

drw

command instead of

rewrite

in

scripts/yosys/synth.tcl

Environment report

openlane.log:ERROR: ABC: execution of command ""/build/bin/yosys-abc" -s -f /tmp/yosys-abc-IhLev5/abc.script 2>&1" failed: return code 134.

71.1.1. Executing ABC.
Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-tRZss0/abc.script 2>&1

ABC: + refactor
ABC: An error occurred during computation. The original network is restored.
ABC: + balance
ABC: + rewrite
ABC: yosys-abc: src/base/abc/abcAig.c:167: void abc::Abc_AigFree(abc::Abc_Aig_t*): Assertion `Vec_PtrSize( pMan->vStackReplaceOld ) == 0' failed.
ABC: Flags A, B, or C are not zero.
ERROR: ABC: execution of command ""/build/bin/yosys-abc" -s -f /tmp/yosys-abc-tRZss0/abc.script 2>&1" failed: return code 134.

Reproduction material Please refer to this for the specific testcase, attached makefile and sources (testcase.zip) to reproduce problem. YosysHQ/yosys#174 (comment) Relevant log output

+ fx 
Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
+ mfs 
+ strash 
+ refactor 
An error occurred during computation. The original network is restored.
+ balance 
+ drw 
+ refactor 
+ balance 
+ drw 
+ drw -z 
+ balance 
+ refactor -z 
+ drw -z 
+ balance 
+ retime -D -D 10000 -M 6 
+ scleanup 
Error: The network is combinational.
+ map -p -B 0.2 -A 0.9 -M 0 
The cell areas are multiplied by the factor: <num_fanins> ^ (0.90).
The cell delays are multiplied by the factor: <num_fanins> ^ (0.20).
+ retime -D -D 10000 
+ &get -n 
+ &st 
+ &dch 
+ &nf 
+ &put 
+ buffer -N 25 -S 750.0 
+ upsize -D 10000 
Current delay (5733.16 ps) does not exceed the target delay (10000.00 ps). Upsizing is not performed.
+ dnsize -D 10000                                                                                                                                 
+ stime -p    

With drw instead of rewrite, ABC works fine

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