I m trying to get systemverilog support working which involv

Question

I m trying to get systemverilog support working which involves using `uhdm yosys instead of `yosys` However when I run `flow tcl` it gives me an error of `invalid command name read systemverilog ` What s the right way to get it working ` `I m setting the binary to `uhdm yosys` using ` SYNTH BIN uhdm yosys ` and I m specifying my own version of `synth tcl` `

Vijayan Krishnan · Answer

To get core team support start your discussion here <https github com The OpenROAD Project OpenLane discussions> Otherway you can pass your netlist directly to OpenLane flow as blackbox to skip yosys based synthesis in the flow

Sean Cross · Answer

Thanks I ll ask questions there

Ilya Lapshin · Answer

< Sean Cross> Did you find a solution

Sean Cross · Answer

I did I m working through a demo here <https github com xobs gf180mcu cpu pizza blob 707e3cbfe7c555fbdc0879c8497f5754205e38a2 j22 synth tcl L221 L229>

Sean Cross · Answer

`yosys import` creates TCL aliases for every possible Yosys command I could change it to run `yosys read systemverilog ` instead of running `yosys import`

Sean Cross · Answer

Note that there is an outstanding issue to remove `yosys uhdm` from conda hdl in favour of just adding the plugin to `yosys but that hasn t been completed yet `