set_db lib_search_path /install/FOUNDRY/digital/90nm/dig/lib

set_db hdl_search_path ./

set_db library slow.lib

read_hdl {code.v}

# In above {code.v}, "code" is the module name. Module name and project name should be same.

elaborate

read_sdc ./constraints_top.sdc

# If only using Combinational Design, remove the above line. Otherwise, don't bother

synthesize -to_mapped -effort medium

write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge > delays.sdf

#In the below lines, "code" is your project

report area > code_area.rep

report power > code_power.rep

report gates > code_gates.rep

report timing > code_timing.rep

write_hdl > code_netlist.v

write_sdc > code_const.sdc

report area

report power

report gates

report_timing -unconstrained