<@U0268926L04> latest openlane flow is breaking in...
# openroadd
Dinesh A
04/04/2023, 3:42 PM@Vijayan Krishnan latest openlane flow is breaking in my Riscduino project at klayout GDS streaming out phase. Do we need to update any addition variable in config file ?
Copy code
[ERROR]: during executing: "python3 /openlane/scripts/klayout/stream_out.py --output /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/results/signoff/wb_interconnect.klayout.gds --lyt /opt/pdk_mpw9/sky130A/libs.tech/klayout/tech/sky130A.lyt --lym /opt/pdk_mpw9/sky130A/libs.tech/klayout/tech/sky130A.map --lyp /opt/pdk_mpw9/sky130A/libs.tech/klayout/tech/sky130A.lyp --top wb_interconnect --with-gds-file /opt/pdk_mpw9/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds --input-lef /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/tmp/merged.nom.lef /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/results/routing/wb_interconnect.def |& tee /dev/null /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/logs/signoff/32-gdsii-klayout.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
Warning: No mapping for layer 'pwell', purpose 'LEFOBS' - layer is ignored
'NoneType' object has no attribute 'cell_index'
child process exited abnormally
[ERROR]: Step(32:gds_klayout) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
while executing
"throw_error"
(procedure "try_exec" line 17)
invoked from within
"try_exec python3 $::env(SCRIPTS_DIR)/klayout/stream_out.py --output $klayout_out --lyt $::env(KLAYOUT_TECH) --lym $::env(KLAYOUT_DEF_LAYER_MAP) --lyp ..."
(procedure "run_klayout" line 22)
invoked from within
"run_klayout"
(procedure "run_klayout_step" line 3)
invoked from withinDinesh A
04/04/2023, 3:49 PMOpenlane details
Copy code
inesha@lenovo-i3-10100-07IMB05:~/workarea/efabless/MPW-9/OpenLane$ python3 ./env.py issue-survey
Kernel: Linux v5.15.0-69-generic
Distribution: ubuntu 20.04
Python: v3.8.10 (OK)
Container Engine: docker v20.10.22 (OK)
OpenLane Git Version: ed194238ac359aca044c54fa8cbbbd12280e1a8c
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)
ed194238 2023-03-29T15:14:23+02:00 Move Timing Checks After Report Generation (#1706) - Mohamed Gaber - (HEAD -> master, tag: 2023.03.30, origin/master, origin/HEAD)
c2944188 2023-03-29T14:34:48+02:00 Revert "#1703" (#1705) - Mohamed Gaber - ()
54d5b5a3 2023-03-29T14:01:00+02:00 Fix regression in #1685 (#1703) - Mohamed Gaber - ()
---
Git Remotes
origin <https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin <https://github.com/The-OpenROAD-Project/OpenLane> (push)v
Vijayan Krishnan
04/04/2023, 4:04 PMShare the config.json. some variables are removed.
d
Dinesh A
04/04/2023, 5:05 PMI have still using config.tcl approach, attached the config.tcl
m
Mitch Bailey
04/04/2023, 9:32 PM@Dinesh A Can you post
/home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/logs/signoff/32-gdsii-klayout.logd
Dinesh A
04/05/2023, 2:54 AM@Mitch Bailey I don't see much info in the log, attached the same
m
Mitch Bailey
04/05/2023, 3:29 AMDid this message occur in your previous successful runs? (if you still have them around).
d
Dinesh A
04/05/2023, 4:51 AMMy setup work with MPW-8 older version of docker. Look like issue is coming from latest klayout tool. Let me try with Different Klayout version. I see couple of Klayout update in git for last three month.
@Vijayan Krishnan I assume my project (riscduino) is part of openroad regression list ?
Dinesh A
04/05/2023, 5:06 AMLook like in openlane klayout/stream_out.py script is newly added in three month back, not sure I see need to update any additional environmental definition in my config.tcl
v
Vijayan Krishnan
04/05/2023, 5:15 AMMPW-CI regression stopped. I am not aware what changes in OpenLane causing this failure. Share your repo link, let me check it
d
Dinesh A
04/05/2023, 5:44 AMI have cross-checked the issue in https://github.com/dineshannayya/riscduino_dcore and Hardening Macro : wb_interconnect. My understanding, the flow will break for any Macro hardening.
3 Views