it's cool it see it's concentrated in the lower chain (and somehow match the characterisation result)
03/29/2023, 1:08 PM
Your error distribution is just the Fibonacci sequence ANDed with the channel status 0 = good, 1 = bad. Channels 0-3, 5, and 7 are simply disabled. Which pins are these on the chip? Does the output bit match the GPIO channel number?
03/30/2023, 12:30 AM
ah sorry for the confusion, the axis are not labeled very well
This actually shows mproj_io[8:37] in the X axis, and fibonacci iteration on the Y axis
so it's not showing other gpios (lower than mproj_io8) , just the expected fibonacci number versus the actual IOs output'ed by the project
I does look like bit0-3,5 and 7 are always at 0 you're right!
There should be a better way of plotting that.
I could also sample those multiple time and see if varies across run :) and then maybe I call that a "distribution"