#1697 Synthesis results can change based on comments or blank lines in Verilog source Issue created by algofoogle Description Depending on how many blank lines (or comment-only lines) I have within the first ~95 lines of my Verilog source, I get different synthesis results (and hence different routing/layout) when running (say)

make MYTEST

to harden my design. There is some wiggle room: 20 blank lines and 30 blank lines give identical synthesis results to each other, but 0 and 40 blank lines do not. This doesn't happen with all source files. I've provided a small example below where it DOES happen: I've got one source file with my top design, and adding blank lines to this makes no difference at all. However, the top design instantiates a module that is defined in another file, and THAT file exhibits this strange behaviour when blank lines are added to it. I think this is a Yosys issue, i.e. it starts with synthesis and straight away I can detect a change in

results/synthesis/MYTEST.v

after Step 1 is complete. (Tested using efabless/caravel_user_project with both

mpw-9a

and

mpw-8c

tags; results vary a tiny bit between tags, but are consistent within the same tag each time). Expected Behavior No matter how many blank lines or comment-only lines there are scattered throughout all included

.v

source files, so long as the material code itself is not changed, then synthesis should remain the same every time if all other variables/parameters remain the same. This stood out as a problem because I didn't change anything else about my already-hardened design, other than to add the SPDX/license header comments to all my files, and then I found this lead to unexpected differences in my final GDS -- which I noticed first because the

routing_layer5_pct

(and others) layer congestion percentage had changed when doing a final-FINAL test. Environment report

Kernel: Linux v5.15.0-67-generic
Distribution: ubuntu 20.04
Python: v3.8.10 (OK)
Container Engine: docker v20.10.12 (OK)
OpenLane Git Version: cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

cb59d1f 2022-11-18T18:42:38+02:00 fix return values in `equally_spaced_sequence` (#1503) - Kareem Farid -  (grafted, HEAD, tag: 2022.11.19)
---
Git Remotes

origin	<https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin	<https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material I cloned efabless/caravel_user_project:

git clone git@github.com:efabless/caravel_user_project
git checkout mpw-9a

Then dropped in contents of MYTEST.tar.gz:

verilog/rtl/MYTEST.v          # Top design; instantiates MYTEST_sub.
verilog/rtl/MYTEST_sub.v      # The file where blank lines change synthesis results!!
openlane/MYTEST/config.json   # Uses the above 2 Verilog files.

I ran:

make MYTEST

I then added 20 blank lines to the top of

MYTEST_sub.v

and ran the make again -- got different synthesis results. I added 10 more blank lines (30 total), and ran the make -- got SAME synthesis results as for 20 blank lines. I added 10 more blank lines (40 total), and ran the make -- got DIFFERENT synthesis results again. Relevant log output

I don't yet know if there's any relevant log output because what we're looking at is a difference between runs; not the outcome of a run in isolation. I will try to add more if I find anything telling, however.

The-OpenROAD-Project/OpenLane