so I'm slowly trying to learn

magic

but I've been busy and I haven't even got a simple inverter working yet. naturally, it got me thinking whether there any analog design paradigms in which one doesn't do the layout by hand. Is there any reason not to lay out an analog design using simulated annealing (SA) based tools similar to the way digital ones are laid out? I reckon a SA tool could, for example, be smart enough to minimize the wire length of nets marked critical by the designer, etc. I realize the noise of such a circuit might be somewhat higher than a handcrafted one but sometimes the design time matters also. does anyone have anything to recommend, or other thoughts along these lines? or is there a good reason to disrecommend such an approach? while searching this I found this interesting tidbit on SE: https://electronics.stackexchange.com/a/60961 it doesn't mention noise levels but since they (were) customizing only the via layer they must have had additional noise from extra tracks and potential interconnection points too

Thanks @Morris Frazier...there are research in progress. How would it automatically provide device parameters???

Analog layout automation has a couple of open source tools where your mileage may vary: 1) BAG3 (https://github.com/bluecheetah/bag3_analog) 2) Laygo2 (https://github.com/niftylab/laygo2) 3) ALIGN (https://github.com/ALIGN-analoglayout/ALIGN-public) But, it is ongoing research and there are a few different approaches, for instance in this survey article there are many techniques listed: https://www.mdpi.com/2079-9292/11/3/435 - these do include simulated annealing. FPAAs have been around since the 80s but never really achieved commercial viability and are still a work in progress (although you can buy a pretty simple ones). I know Hasler at Georgia Tech is pushing hard to have these adopted and has released some open-source tool to interact with her own SoC FPAA (https://woset-workshop.github.io/PDFs/2020/a18.pdf).