When I'm creating a design using hierarchical option, like in this case, a buffer made by 2 inverters, do I have to create new layers for top ports, power rails and internal connections [Fig 1,2]? Also, do I have to add labels to the inputs, outputs, VPWR, VGND?

yes, or it might not pass LVS

You will need port labels for the top-level cell ports including power and ground. They do not necessarily need additional layers, but you are less likely to run into problems with extraction and LVS if you have each port label attached to a piece of metal in the same (top level) cell. The only specific rule for having labels by themselves without metal is that you need to manually assign the label to a layer and set the "sticky" option, both of which can be done from the text GUI window.