@Stefan Schippers xschem bus notation is extremely useful (https://xschem.sourceforge.io/stefan/xschem_man/tutorial_busses.html) But how to use the special ground pin (0) in the bus notation? i.e., I want my bus to be "RST,8*0", where 0 is repeated 8 times. It seems this syntax is not supported. How to do it properly?

Has anyone experience with running ngspice on a mac (M1)? Everything works fine, except that I cannot get the plotting function to work (homebrew installation). Error message:

Can't open viewport for graphics.

I have XQuartz (2.8.2 ) installed and other plotting tools (e.g., gnuplot) work fine. Seems that ngspice cannot connect to XQuartz somehow. Any help is appreciated!

Getting [ERROR PSM-0042] Unable to connect macro Instance to the power grid. Is there any change in the syntax of FP_PDN_HOOKS in config.json

Hi While using GPIO as analog pins what should be the condition for io_oeb and in which file we need to specify the io_oeb condition.

Hi, I have an issue regarding setting constraints with hierarchical paths. I believe the issue is caused by Yosys flattening the netlist and not regenerating the SDC constraints with the updated paths. This is then causing the constraints to not be recognized as many of the signals were renamed and the hierarchy was lost. Not flattening the netlist doesn't fix the issue either. By default Yosys doesn't seem to have the feature to rewrite sdc constraints, I've tried using the following plugin: sdc-plugin for Yosys, which adds support for read_sdc and write_sdc, but the generated SDC constraints are also based on the pre-synthesis RTL (not compatible with the post synthesis netlist). This is causing issues in the flow since STA is not able to recognize the timing constraints. Adjusting the constraints manually to match the post-synthesis netlist seems to work, however, the netlist is quite large and there are many SDC constraints so that is not really feasible for my project. Is there a solution to this other than adjusting the SDC constraints according to the post synthesis netlist?

Hi, During the LEC step between the Yosys-synthesized netlist and the GL netlist, I am receiving warnings about the following cells: 1.

sky130_ef_sc_hd_decap_12

2.

sky130_fd_sc_hd_fill_1

3.

sky130_fd_sc_hd_tapvpwrvgnd_1

Since these cells are used to reduce DRC violations, maintain power rail continuity, and reduce IR drop, they likely have no logical function. I assume these warnings are not significant in terms of LEC. I can comment out the related lines containing these cells from the Yosys netlist and perform LEC later, where it succeeds. I would appreciate your thoughts on this issue.

any suggestion or solution to fix it, thanks

Hi how re u? Im triying to port the SAR ADC form this pdf https://epub.jku.at/obvulihs/content/titleinfo/8694768 and i have a problem with de the preamplifier, the thesis uses SKY130, and im trying to do in gf180, so i tried to keep some ratios between the width form the mosfet. My question is: -How to improve the preamp´s gain? cascaded preamp? -why when a transistor gets polarized (i think its actually cutoff) it makes the another out´s capacitor gets discharged faster?

Hi all. I wanted to ask that is there a way in openlane to add a vcd file of design to estimate power. Thanks

I can't figure out how to import the netlist, and also how to integrate it with the caravel project