grmbl if I have

m.xx1.xm1.msky130_fd_pr__nfet_g5v0d10v5#body

in ngspice, isn't

@m.xx1.xm1.msky130_fd_pr__nfet_g5v0d10v5[id]

the drain current?

save @m.xx1.xm1.msky130_fd_pr__pfet_g5v0d10v5[id]
op
print all
Error(checkvalid): vector @m.xx1.xm1.msky130_fd_pr__pfet_g5v0d10v5[id] is not available or has zero length.

Such a PITA to get any transistor parameters out of this thing

Hello guys, I am trying to run a ring oscillator through openlane and it keeps simplifying my design, is there a way to tell it to not simplfy the design?

I can't validate my shipping address: "Unable to validate address through our shipping provider. Code: STANDARDIZED.ADDRESS.NOTFOUND". Someone help me?

@User @User @User I am progressing on my MPW-5 tapeout, but I have a fail in min. density on LI1 (the only fail left in the TO procedure). Here now a couple of issues: • I look at the final oasis file (

caravel_00054fe4.oas

). By inspecting I find that the filling structures are on purpose 28, which is not documented here: https://skywater-pdk.readthedocs.io/en/main/rules/layers.html?highlight=28#gds-layers-information and not here: https://skywater-pdk.readthedocs.io/en/main/_downloads/b4838a38f1379533883c717f8f86d7b2/gds_layers.csv — Someone should please complete the layer docs in the above references. • When I look at the layers 56:0 and 56:28 then I find that the filling structures are there on 56:28, but nothing on 56:0 (CLI1M). However, the layer 67/20 (LI1 drawing) is really full. As I have no idea how I could increase density (and anyway it is automatically generated), I have the impression that the density calculation might be wrong, not taking into account filling plus user structures? Could this be?

@User @User I tried to reproduce the DRC issue w/ OpenRAM v1.1.19, and the flow worked for me w/

open_pdks.sky130a-1.0.286_0_g52af776

and

magic-8.3.257_0_gc8c8f8b

(see this notebook https://colab.research.google.com/gist/proppy/207020434aa0ff38bfd89eb97a4d4f59/openram-playground.ipynb) is there something special to do to enable the DRC check? (it printed

DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).

so I'm not sure how extensive the current testing is?)

I have a question about the memory readout delay. In the SRAM behavior model (.v) it sets a default delay value to be 3ns, but I checked the library file (.lib) it seems like the delay for the dout port is about 0.3ns~0.5ns, which looks like a registered output. I think I should trust the lib file but just want to double confirm that the delay for the SRAM read out is roughly at the scale of <1ns range

xschem reading Ngspice simulation data directly. Now need to add some UI for zooming / panning, waveform displaying is lightning fast! The bottom circuit draws / zooms at 42 fps with all waveforms loaded. The 8MB .raw file is read in 17ms.

Hi All, I am trying to run ngspice for a .spice generated through xschem as a test run and getting these errors < Error: could not find include file ../../libs.ref/sky130_fd_pr/spice/sky130_fd_pr__nfet_01v8__tt.corner.spice ERROR, library file /user/local/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice, section definition tt not found ERROR: fatal error in ngspice, - Can someone please help me to understand what's happening ?

Hi all, I have encountered a Klayout FEOL DRC error during the precheck of my design. However, I found no drc violation when doing drc check in klayout on the gds. I have read the FEOL report but I don't understand the meaning of the error. I tried to locate those errors on the gds file, but all 5 errors are pointing to the empty area. Could anyone help me? gds file is here: https://github.com/jhz701/class_d_audio_amplifier/tree/main/gds

I am having an error in the openlane flow can anyone give me a solution for that im getting this error while running make user_proj_example