@Mitch Bailey I am facing FEOL , BEOL errors in local precheck and trying to rectify them. Is there any way in local precheck to run only these specific checks and skip other checks in order to save time.

Hello, I'm encountering issues with the OpenLane flow. Upon executing the command "flow.tcl -design ../top -tag test1", I encounter a problem that I've been unable to resolve. This is puzzling, as a previous module ran successfully. However, after incorporating this module into the top design without significant modifications, the aforementioned error arises.

What is the difference between nfet_01v8_lvt and nfet_01v8_lvt_nf?

Hello Everyone, Magic reading GDS files: Magic throws some errors when reading our large Caravan GDS file. The errors are below:

Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
Error while reading cell "LNA" (byte position 667929024): Warning:  Cell LNA boundary was redefined.
CIF file read warning: Input off lambda grid by 1/5; snapped to grid.

If I flatten the GDS, then Magic reads it no problem. With no errors. I would like to maintain higherarchy for LVS extraction so would anyone have any recommendations on what is causing the errors and how to resolve them? Thanks a lot!

How Can I put the body mosfet contact in magic analog layout?

HI , getting below error suddenly from yesterday... no other process running on the machine strangely magic runs/trial2_mac/tmp/floorplan/6-pdn.def X Error of failed request: BadAlloc (insufficient resources for operation) Major opcode of failed request: 53 (X_CreatePixmap) Serial number of failed request: 18915 Current serial number in output stream: 18958

I'm having an issue when trying to make caravel user_project_wrapper during Detailed Routing.

[ERROR DRT-0305] Net one_ of signal type POWER is not routable by TritonRoute. Move to special nets.

Error: droute.tcl, 46 DRT-0305

child process exited abnormally

What could be causing this error?

Hi @Mitch Bailey, I'm attempting to make a simple inverter to get familiar with the opensource workflow but getting stucked with LVS. Current situation is the circuits and netlists match but the subcircuit pins does not. The columns under the subcircuit pins has another duplicate of pin names while the other has no matching pin. The layout spice file is generated with ext2spice hierarchy on. I'm not sure whether I'm doing LVS correctly nor how to correct it. Please find the Netgen LVS output, comp.out, spice files for inverter layout(CMOS_INV) and schematic (INV_VP_VN) in the attachment. Thanks in advance!

Hello everyone. How can I simulate Noise figure and OIp3 with NgSpice?

The sky130A.lydrc in open_pdks cannot be used in batch mode for klayout when I use the following command:

klayout -b -rd input=my_layout.gds -rd report=sky130_drc.txt -r drc_sky130.drc

The drc_sky130.drc is renamed from sky130A.lydrc. It reports a series syntax errors due to the header of the XML, So I commented them out, and there are other syntax error derived from XML, such as

&

symbol. Should I just replace those symbol with plain text symbol

&

or there is other dedicated file for running klayout in batch mode? @Tim Edwards