I am loading a raw file from a noise simulation that has the following variables:

tcleval([xschem raw list])

@Matt Venn @Anton Maurovic (efabless support) i want to use the LA pins in caraval as follows la118:113 control signal to user area analog_io16 or mprj_io 26 =3.3V analog_io17 or mprj_io 27 =GND VSS TO GND ANALOG_IO12 OR MPRJ_IO 22 =3.3V ANALOG_IO15 OR MPRJ_IO25 =1.8V LA40 DAC_WL_DOWN =low ( user area control signal) LA48 DAC_WL-UP =HIGH ( user area control signal) ANALOG_IO0 OR MPRJ_IO10 OUTPUT .attached is the code but the output is not correct, could u pls help as its my first LA control program

Script seems to work for metals, please check on your designs. 1. Update the variable

user_space

on the

main_*

functions to reflect the area of the chip. I'm testing without the padring. 2. Open the design on Klayout 3. Add script directory to Macro Development and execute it. (

Macros --> Macro Development --> Ruby --> Add Location

) I'm working on fix COMP errors now.

readline: readline_callback_read_char() called with no handler! Thread 1 "xschem" received signal SIGABRT, Aborted. ... HEAD~5a4b2cc6~20240425 built with readline-7.0-10.el8.x86_64 tcl-tclreadline-2.1.0-16.el8.x86_64 (gdb) bt ... #12 0x00007ffff65b7927 in Tcl_GlobalEval () from /lib64/libtcl8.6.so #13 0x000000000048d815 in tcleval (str=0x527268 "text_line {Input property:} 0 normal") at scheduler.c:6051 #14 0x00000000004ad811 in edit_wire_property () at editprop.c:1038 Triggered this one a few times, wasn't sure how/why, rebuilt in debug mode, no issues for a few days 🙂 finally triggered it, but now I think it can be reproduced on demand Step are something like, open .sch, find/select a symbol, edit attributes (on symbol), change .sym file to non-exist file by removing directory component to path, click OK, use tclreadline stdin Go back reselect symbol, edit attributes (on symbol), change .sym file to be prefixed with ./ but do not press OK, then go back to use tclreadline stdin and find it SIGABRT (with edit_properties dialog window open)

for lvs, do transistors have to be the right way round? I have this

XM1 osc_a osc_b left_cap VSS sky130_fd_pr__nfet_01v8

for schematic and this

XXM1 osc_a VSUBS osc_b left_cap sky130_fd_pr__nfet_01v8_L9BG78

for layout.

I have added a nice cheatsheet (also available as a schematic in

devices/intuitive_interface_cheatsheet.sch

) for the recent additions of 'click and drag' interface (Enable it in

Options -> Intuitive Click & Drag interface

). This mode can be enabled permanently by setting

set intuitive_interface 1

in the

xschemrc

file. https://xschem.sourceforge.io/stefan/xschem_man/intuitive_interface_cheatsheet.svg

Hi, can anyone please tell me the the difference between GPIO_MODE_USER_STD_ANALOG and GPIO_MODE_MGMT_STD_ANALOG? I know that the MGMT_ENABLE pin is high for the later one. But what difference does it make regrading input, output buffers and leakage?

Regarding Klayout FEOL and BEOL DRC violations on the pre-check, where is the best place to correct these? Directly in the user_project_wrapper.gds which Openlane generates, or in the .gds of the Macro we are feeding to Openlane to build (or does it not really matter?)

Hello, I'm encountering issues with the OpenLane flow. Upon executing the command "flow.tcl -design ../top -tag test1", I encounter a problem that I've been unable to resolve. This is puzzling, as a previous module ran successfully. However, after incorporating this module into the top design without significant modifications, the aforementioned error arises.

@Stefan Schippers Trying to plot Id-Vd curve for NMOS with sweeping Vgs. But not able to plot waveform inside xschem window. Please see attached gif file and suggest what might be wrong here.