xschem can't load the raw sim data on startup as its path is wrong. After running simulation, the path is fixed and it can load it

Hi, Can you please tell if Open Ram support banks right now @Matthew Guthaus? When I tried to run by putting "num_banks = 2" in config file , I got error saying "bl0 net is not found in timing paths"

Hello! I'm trying to run

make user_project_wrapper

and I keep getting this error:

[STEP 21]
[INFO]: Creating IR Drop Report (log: ../home/mc/encryption_caravel_user_project/openlane/user_project_wrapper/runs/23_12_03_22_34/logs/signoff/21-irdrop.log)...
[WARNING]: VSRC_LOC_FILES is not defined. The IR drop analysis will run, but the values may be inaccurate.
[ERROR]: during executing openroad script /openlane/scripts/openroad/irdrop.tcl
[ERROR]: Log: ../home/mc/encryption_caravel_user_project/openlane/user_project_wrapper/runs/23_12_03_22_34/logs/signoff/21-irdrop.log
[ERROR]: Last 10 lines:
Worstcase voltage: 5.00e+00 V
Average IR drop  : 1.02e-06 V
Worstcase IR drop: 6.54e-06 V
######################################
[INFO PSM-0022] Using 5.000V for vccd2
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[INFO PSM-0031] Number of PDN nodes on net vccd2 = 708.
[ERROR PSM-0042] Unable to connect macro/pad Instance mprj to the power grid.
Error: irdrop.tcl, 35 PSM-0042
child process exited abnormally

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...

and issue_reproducible is here. Any help would be great,thank you!

hey all, i'm unable to get

make setup

to work when cloning the

gfmpw-1c

branch (as mentioned here https://efabless.com/gf-180-open-mpw-shuttle-program) it fails with this:

kris@kris-desktop:~/repos/diy-ic/caravel_user_project$ make setup
/bin/sh: 1: cd: can't cd to verilog/dv/cocotb
/bin/sh: 1: cd: can't cd to verilog/dv/cocotb
Makefile:100: warning: undefined variable 'CARAVEL_NAME'
Makefile:101: warning: undefined variable 'CARAVEL_TAG'
Makefile:101: warning: undefined variable 'CARAVEL_REPO'
if [ -d "/home/kris/repos/diy-ic/caravel_user_project/caravel" ]; then\
        echo "Deleting exisiting /home/kris/repos/diy-ic/caravel_user_project/caravel" && \
        rm -rf /home/kris/repos/diy-ic/caravel_user_project/caravel && sleep 2;\
fi
echo "Installing .."
Installing ..
git clone -b   /home/kris/repos/diy-ic/caravel_user_project/caravel --depth=1
fatal: You must specify a repository to clone.

any help would be great, thank you :)

Do the corner simulations ss,ff,fs,sf model the resistor and cap variations with process.

Hello I'm trying to use a spice model from Mos from SkyWater PDK on LTspice, but it doesn't work. However, I have successfully used a mos model(BSIM4) from https://ptm.asu.edu/. I call the file where is the model but when I launch the simulation there are an error who said " this model doesn't exist". I used probably the wrong name ?! Do you know how used this model (from Skywater) on LTspice ? I use this file sky130_fd_pr__nfet_01v8_lvt.pm3.spice. Is it the good one ? The netlist for this component is : M1 N001 Vg1 0 0 sky130_fd_pr__nfet_01v8__model l=150n w=0.15u Thanks you for your help.

Can anyone help me with this? Having trouble installing magic +sky130 pdk.

Hi, ALL I am just starting to understand how OpenRAM works with sky130 pdk by following the OpenRAM Github document below https://github.com/VLSIDA/OpenRAM But stacked on ERROR as you can see attached screenshot, can someone advise me to find a way to cleanup it? Thank you… I would like to share what I made below. 1. Cloned OpenRAM

$ git clone <https://github.com/VLSIDA/OpenRAM.git>

2. Build docker tool

$ cd OpenRAM/docker
$ make build

3. export below.

$ export OPENRAM_HOME="$HOME/OpenRAM/compiler"
$ export OPENRAM_TECH="$HOME/OpenRAM/technology"
$ export PYTHONPATH="$OPENRAM_HOME:$OPENRAM_TECH/sky130:$OPENRAM_TECH/sky130/custom"

4. edit myconfig.py as following

# Data word size
word_size = 8
# Number of words in the memory
num_words = 128
num_rw_port = 2  # In case "1" generate ERROR
tech_name = "sky130"
nominal_corner_only = True
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

5. Compile it

$ cd OpenRAM
$ make pdk
$ make install
$ python3 $OPENRAM_HOME/openram.py myconfig

6. Stucked with attached ERROR.

Hey folks, how do I load the magic sky130 pcell generator? I'm running a clean install of sky130 (I know of the docker, but I want to try to create a working OS RF design environment) and the sky130A.tcl doesn't load

My complete design will be digital-on-top but I also have analog components that I want OpenLane to route together with the digital parts. Can anyone provide me with an outline of how to do this please?