For some reason, the generated netlist for user_project_wrapper in my case has register declarations between port declarations like the following.
module user_project_wrapper(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_sel_i, wbs_dat_i, wbs_adr_i, wbs_ack_o, wbs_dat_o, la_data_in, la_data_out, la_oenb, io_in, io_out, io_oeb, analog_io, user_clock2, user_irq);
reg \$auto$<http://verilog_backend.cc:2083:dump_module$57|verilog_backend.cc:2083:dump_module$57> = 0;
reg [31:0] _00_;
reg [31:0] _01_;
reg [31:0] _02_;
reg [31:0] _03_;
reg [31:0] _04_;
reg [31:0] _05_;
reg [31:0] _06_;
reg [31:0] _07_;
reg [31:0] _08_;
reg [31:0] _09_;
reg [31:0] _10_;
reg [31:0] _11_;
reg [31:0] _12_;
reg [31:0] _13_;
reg [31:0] _14_;
reg [31:0] _15_;
wire [8:0] _16_;
wire [8:0] _17_;
wire [8:0] _18_;
wire [8:0] _19_;
...
wire [31:0] _62_;
wire [31:0] _63_;
inout [28:0] analog_io;
wire clock;
input [37:0] io_in;
output [37:0] io_oeb;
output [37:0] io_out;
This causes the following syntax error after synthesis.
[ERROR STA-0164] /home/aanujdu/tapeout_modulonet/caravel_user_project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user _project_wrapper.v line 4, syntax error, unexpected REG
STA-0164
[ERROR]: during executing openroad script /openlane/scripts/openroad/sta.tcl
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
The user_project_wrapper in my design only instantiates two macros, i.e., no std cells at the top level. So I am not sure why would Yosys synthesize it like this. Has anyone faced this before and knows a possible fix?
