Hi All, I am a recently retired Analog / Mixed Signal circuit designer. I have been trying to set up my home Linux workstation to run all these open source cad tools and the Sky130 pdk. As expected of an old fart like myself, I am having difficulty with the downloads. Would someone point me to the correct repository and the correct scripts in order to download and install the open source cad tools and the Sky130 pdk. I have a new linux workstation running the Ubuntu 20.04 operating system. Your help is greatly appreciated.

Is your setup file correct?

.../netgen/sky130A_setup.tcl

Check your netgen output for error messages (ie. can't find file, etc.) Also, I recommend putting the layout netlist first and the schematic netlist second. From the setup file.

# NOTE:  In accordance with the LVS manager GUI, the schematic is
# always circuit2, so some items like property "par1" only need to
# be specified for circuit2.

I'm trying to run MC simulations with ngspice and the results are repeating. I don't know why. Here is my circuit

* Monte carlo test

* Include SkyWater sky130 device models
.lib "/usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
.param mc_mm_switch=1

.include "../aux/array.spice"
.include "../aux/inv.spice"

.param pVDD = 3.3

VDD  vdd 0 dc {pVDD}
VSS  vss 0 0

x0 q q vdd vss inv1_1

.option seed=random
.control
	echo # Monte carlo run > mc.txt
	let run = 1
	dowhile run <= 100
		reset
		op
		print q
		let q = v(q)
		echo $&run $&q >> mc.txt
		let run = run + 1
	end

.endc

.end

and my results

# Monte carlo run
1 1.60672
2 1.60672
3 1.60672
4 1.6164
5 1.6164
6 1.6164
7 1.6164
8 1.6164
9 1.61179
10 1.61179
11 1.61179
12 1.61179
13 1.61179
14 1.61632
15 1.61632
16 1.61632
17 1.61632
18 1.61632
19 1.61632
20 1.61632
21 1.60583
22 1.60583
23 1.60583
24 1.60583
25 1.60583
26 1.60583
27 1.61683
28 1.61683
29 1.61683
30 1.61683
31 1.61683
32 1.61683
33 1.61683
34 1.61374
35 1.61374
36 1.61374
37 1.61374
38 1.61374
39 1.61631
40 1.61631
41 1.61631
42 1.61631
43 1.61631
44 1.61631
45 1.61631
46 1.61606
47 1.61606
48 1.61606
49 1.61606
50 1.61606
51 1.61606
52 1.6167
53 1.6167
54 1.6167
55 1.6167
56 1.6167
57 1.6167
58 1.61162
59 1.61162
60 1.61162
61 1.61162
62 1.61162
63 1.61162
64 1.61162
65 1.61726
66 1.61726
67 1.61726
68 1.61726
69 1.61726
70 1.61726
71 1.61863
72 1.61863
73 1.61863
74 1.61863
75 1.61863
76 1.61863
77 1.60948
78 1.60948
79 1.60948
80 1.60948
81 1.60948
82 1.60948
83 1.60948
84 1.61978
85 1.61978
86 1.61978
87 1.61978
88 1.61978
89 1.61978
90 1.61307
91 1.61307
92 1.61307
93 1.61307
94 1.61307
95 1.61307
96 1.61317
97 1.61317
98 1.61317
99 1.61317
100 1.61317

I have a weird spice problem, where changing the transient simulation from 40us to 400us completely changes the output waveform

Hi all, I'm trying to install ihp open pdk in a docker container using the scripts on iic-osic-tools repo. Some questions arise • Is the compilation of the

.va

files into

.osdi

required to use the pdk? • Compilation of openvaf fails, and using the shared executables crash when using on

<http://psp103_nqs.va|psp103_nqs.va>

. How can I debug this? Or is it documented somewhere? Thanks for the effort put into making another free and open source PDK alternative 🙂

For Varactor, Xschem has three port (as attached). In magic its a PMOS. So, to make right connection in layout, which part of PMOS will be b, c0, c1 like in schematic? Thanks in advance!

After 15 months since the announcement: what is the status of sky-S90? Any timeline? (we know that sky-RH90 is subject to strict ITAR rules and therefore cannot be open source)

Hello. I have a Question about the Synthesis in OpenLane. My Design has 2 inputs clk1 and clk2 . When I did synthesis on OpenLane. Synthesis gets fails every time. But this design works properly after synthesis using Cadence Genus. I have tried 2 possibilities in config file the screenshots are attached below. Anyone knows How to do synthesis using 2 input clocks in Openlane. This is my first post/message so errors may be expected.

What's the difference between sky130A and sky130B? I thought sky130B just added reram blocks, however my design uses no reram yet it fails LVS when I build with sky130A.

Hi , i have created a verilog wrapper file with my analog macro inside it...And in the openlane i am feeding the LEF , LIB and GDS....But flow errors out... The LEF is written from magic. What i suspect is that the tool is not able to TAP the pin Any guidelines on how to create pins of the macros ?? particular width / hegith needed ?? LMK what are all info /files required [STEP 19] [INFO]: Running Global Routing... [INFO]: Starting FastRoute Antenna Repair Iterations... [STEP 20] [INFO]: Running Fill Insertion... [STEP 21] [INFO]: Writing Verilog... [STEP 22] [INFO]: Running Detailed Routing... [ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl [ERROR]: Exit code: 1 [ERROR]: full log: designs/AMUX_wrapper/runs/RUN_2022.08.28_12.23.54/logs/routing/22-detailed.log [ERROR]: Last 10 lines: [INFO DRT-0033] via2 shape region query size = 1920. [INFO DRT-0033] met3 shape region query size = 1454. [INFO DRT-0033] via3 shape region query size = 1920. [INFO DRT-0033] met4 shape region query size = 511. [INFO DRT-0033] via4 shape region query size = 16. [INFO DRT-0033] met5 shape region query size = 26. [INFO DRT-0165] Start pin access. [ERROR DRT-0073] No access point for U_AMUX_8x1_20_08_layout/V4. Error: droute.tcl, 46 DRT-0073 child process exited abnormally