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Hi <@U016EM8L91B>, After solving the two problems that you helped me with in the other threads, now ...
# magic
j
Hi @Tim Edwards, After solving the two problems that you helped me with in the other threads, now I wanted to apply that in a ring oscillator, to obtain the LVS, but I have a problem, although the devices match me, I have a problem with the pins, unlike the another one that was an internal cell, here in xschem I disabled the LVS netlist, but the design in mag if I flattened it as you mentioned, do you still know what the problem could be?
inverter_blo_mag.spiceinverter_blo.spice
comp.out
m
@Juan Andres Looks like 
inverter_blo.spice
and 
inverter_blo_mag.spice
are the same file. Anyways, you need to add some pin/text layers to the top level layout.
j
Well, I wrote label VDD and label GND, but it doesn't add them in the extraction, why?
cc.JPG
m
There are pin layers and text layers. I’m not sure what the tech file recognizes as pins with your version of the pdk. Take a look at the inverter layout that passed LVS and see what layer the pins/text are on.
j
How can I look at that?
cc.JPG
You are right, it is as if you did not define the top pins, although I assign the label, do not create them, it is strange because they are the same as the one that passed the LVS
m
Is there a pin layer? You might need a text layer and a rectangular pin layer for ports.
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