and you can also see hsync, r & b channels, and the pixel clock on the top

That is possibly the first test of the wishbone interface between the processor and user project?

Maybe so, I haven't seen any other. Ive updated the doc as a success for wishbone write. Yet to try a read

@Matt Venn what is your user pad switching rate ? My case I see User Mode Pad Rise time as bad as 900ns. In Caravel GPIO test case, I see Rise and Fall Time with-in 100ns

@Dinesh A: The user output mode is easiest to set up by using the weak pull-down mode. So by default, user outputs will have a slow fall time. A slow rise time is indicative of an incorrect configuration---the weak pull-up and pull-down modes differ by a bit-shift, so it's fairly easy to get it into that state. For users who need to run faster than the weak-pull modes will allow, there are usually ways to tweak the configuration to get some of the output channels to run full-swing.

@Tim Edwards Yes; I am selectively able configure some of the pad in full swing. Issue in Quad SPI mode; where i need to all the 5 (Clock + 4 Data pin) consecutive pad in fast swing. Currently I am moving ahead with keeping QSPI interface in less than 1Mhz.

@Matt Venn @Konrad Beckmann we're trying to compile feedbacks from the MPW-2 bring-ups, do you have a picture and a quote/testimonial that you'd be ok to share?

quote: "The Zero to ASIC course submitted 16 designs on one chip to MPW2. We've now seen 6 designs at least partially working. Due to the limitations in the IO setup, only the simplest designs are fully functional."