Hi guys! I have the top block of my circuit (device-complete) and a can run the simulation (it takes a few minutes, but runs correctly). So i'm trying to put my circuit into a user_wrapper. First question is: that file comp.out is from LVS. It means the LVS is ok? I see "pins equivalent" and "devices equivalent" in the final lines. But i don't understand the "Final result: Verify: cell ../xschem/simulation/user_analog_project_wrapper.spice has no elements and/or nodes. Not checked." I left some pins open because i did not need them. Second question is: when i change my device on test bench to my user_wrapper (with my device-complete inside), there are some errors (ngspice.txt). What should be?

@Hugo Dias For LVS, you want to use a spice file that has the top block defined as a

.SUBCKT

. Before creating the netlist from xschem, select

Simulation

->`LVS netlist: Top level is a .subckt`

I did that, but happened the same.

@Hugo Dias Can you post the netgen command you’re using?

@Hugo Dias Thanks for reporting. Can you post your spice files here? Also, what version of netgen are you using?

netgen -batch

And what’s the pdk version?

cat $PDK_ROOT/sky130A/SOURCES

If you’re using volare,

volare

.

i dit:

extract all

ext2spice lvs

ext2spice

on my of

user_analog_project_wrapper.mag

with my device inside it.

Check the properties on

user_analog_project_wrapper

. Does

property LEFview

return anything in magic? If it’s set to

TRUE

, you probably want to set it to

FALSE

.