<@U01EPAN5N57> Thanks! I talked to Derek a little ...
# sdram
@taylor-bsg Thanks! I talked to Derek a little last week and understood why it was organized like that. @Derek Hines-Mohrman So I did an in depth read of your circuitry this week, and everything panned out quite elegantly! I was wondering how you amplified the receiver side since SSTL 15 swings only +- 0.175 volts on the centered at 0.75V. If I'm understanding correctly, you're using 2x standard clock buffers to amplify that swing into rail to rail. The only concern I have is on PVT variations of those clock buffers (especially process), which could shift it off center and mess up the result amplification. Were there any simulations on that/measures deployed to calibrate? or we're hoping most of the chips should work 😅