Hi all, I created a small example for simulating the ReRAM cell using xyce and xschem. https://github.com/barakhoffer/sky130_xyce_reram I did some small changes to the Verilog-A model to compile it and added an option to change the initial state of the device. Here is a screenshot from the xschem example (It also uses some ngspice/xschem hacks to load the I-V curve of the PWL simulation 😀)