Thanks for the chat, @User Current status of our evaluation on ASIC + breakout setup is listed for others to follow: 1. ported the iceBreaker verilog to another CPLD board only driven by schedule (iceBreaker is on backorder and we have ordered-- waiting eagerly). 2. found the voltage sources were noisy on the breakout board and added caps to help quiet the noise 3. moved reference verilog sources from pdm to pwm as part of supply noise because the CPLD board did not immediately support pdm IP block natively 4. next step is to determine the state changes from control.py that appear to be unreliable in our tests wherein test-to-test does not follow run-to-run (e.g., vdd-scan to vdd-scan vs vdd-scan to io-mapper) <anyone> Please let us know if this path has been already traversed to understand the cause for vdd-scan behavior difference to fw-load (or io-mapper). NOTE: These ASIC boards remain under debug, it is possible the manufacturing is problematic (soldering, etc.) so there are many avenues under debug and there are no assumed issues with any of the tools/scripts at this point. Given the yield, it is more likely assembly defects at this point.