Thanks! Some issues I have found: • lib file has multiple definitions for the bus types. for example, here is RAM8x32:

type (bus_3_0) { 
   base_type : array ; 
   data_type : bit  
   bit_width : 4   
   bit_from : 3  
   bit_to : 0 ; 
   downto : true ; 
 } 
 type (bus_31_0) { 
   base_type : array ; 
   data_type : bit  
   bit_width : 32   
   bit_from : 31  
   bit_to : 0 ; 
   downto : true ; 
 } 
 type (bus_2_0) { 
   base_type : array ; 
   data_type : bit  
   bit_width : 3   
   bit_from : 2  
   bit_to : 0 ; 
   downto : true ; 
 } 
 type (bus_31_0) { 
   base_type : array ; 
   data_type : bit  
   bit_width : 32   
   bit_from : 31  
   bit_to : 0 ; 
   downto : true ; 
 }

notice how bus_31_0 is defined twice. this causes issues for synopsys lc when reading in the lib file. • in lib file, VPWR and VGND are defined as signal pins

pin(VGND) { 
        direction : input ;
        max_transition : 2.5;
        capacitance : 0.001; 
    } 
    pin(VPWR) { 
        direction : input ;
        max_transition : 2.5;
        capacitance : 0.001; 
    }

these should be pg_pin instead of pin, and have primary_power and primary_ground