Hi, I try to include a 256x32 memory constructed by DFFRAM in a little RISCV and synthesize it via OpenLane. As it got stuck while reading the LEF file, I noticed the constructed file is arbout 100 MB and wondered if this is intended. I use the latest version with 'python3 dffram.py -p $PDK_ROOT -s 256x32' and the flow finishes successfully as far as I can judge. As next step I include it in my verilog design and use the variables 'SYNTH_READ_BLACKBOX_LIB', 'VERILOG_FILES_BLACKBOX', 'EXTRA_LEFS' in the openlane config file. Any hints or improvements are appriciated, thanks in advance.