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Ryan R

01/19/2022, 11:23 AM
Hi , I am trying to run xyce AMDS simulation with veriloga file. The run commands is : export XYCE_ADMSDIR=$XYCE_SRCDIR/utils/ADMS admsXml -x -e $XYCE_ADMSDIR/adms.implicit.xml -e $XYCE_ADMSDIR/xyceVersion_nosac.xml -e $XYCE_ADMSDIR/xyceBasicTemplates_nosac.xml -e $XYCE_ADMSDIR/xyceAnalogFunction_nosac.xml -e $XYCE_ADMSDIR/xyceHeaderFile_nosac.xml -e $XYCE_ADMSDIR/xyceImplementationFile_nosac.xml model.va But errors are being flagged : [info...] -x: skipping any implicit xml scripts [info...] admsXml-2.3.7 (2097728) Dec 21 2021 00:12:23 [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:83]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:104]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:118]: 'item' bad attribute [info...] Top-level analog/code assigns to 0 variables. [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:576]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:1513]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:1522]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:2382]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:2551]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:2578]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:2631]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:2883]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:2894]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:3229]: 'item' bad attribute [error..] [./utils/ADMS/xyceImplementationFile_nosac.xml:3240]: 'item' bad attribute [info...] elapsed time: 0 (second) [info...] admst iterations: 28621 (4922 freed) My model.va is very simple resistor : `include "constants.vams" `include "disciplines.vams" module va_resistor(p,n) ; parameter real resistance = 1000.0 from (0.0:inf] ; electrical p, n ; analog I(p,n) <+ V(p,n)/resistance ; endmodule Any help is appreciated. Thanks!