From the email to the skywater-pdk mailing list from Adam Megacz Joseph:

Hi, I have a few questions about the materials posted in the
skywater-pdk repository for the "google" account on github:

1. Where can I find the design rules for vias and contacts?
   The critical dimensions (i.e. minimum width) and spacing
   are in the CD table, but for vias and contacts there are
   many more rules: at the very least there are rules about
   how much metal on the layers above and below must surround
   the via, and usually there are multiple cases (square,
   rectangular, etc).  There are usually also a separate
   set of rules for "large" arrays of vias (usually 3x3 and
   above) which need more than minimum inter-via spacing.

   Attached below is an example of what I'm talking about,
   taken from the MOSIS SCMOS PDK.  Can you tell me where
   to find the equivalent description in the SkyWater130
   PDK?

2. I assume the term "periphery" refers to the pad ring; is this
   assumption correct?

3. Related to #1 and #2: for many important rules, only the
   "in the periphery" rule seems to be in errors.csv.  Here's an
   example:

     $ grep licon1 errors.csv | grep diff | grep enclosure
     r717,licon.5a,"0.04 min. enclosure of ""licon1"" in periphery by
     diff"
     r719,licon.5c,"0.06 min. enclosure of adj. sides of ""licon1"" in
     periphery by diff"

     $ grep licon1 errors.csv | grep diff | grep enclosure | grep -v
     periphery

   The second grep command yields no results -- errors.csv is missing
   the non-periphery rule for enclosure of licon1 by diff.  I found
   many other examples of rules where only the "in periphery" form
   had an entry in errors.csv.  Are there other rules that aren't
   represented in errors.csv?   

3. Also related to #1 and #2: many of the via rules include the phrase
   "enclosure of adj. sides".  Shouldn't this be "enclosure of OPPOSITE
   sides"?  Most commercial foundries (at least ~180nm and later on ST,
   UMC, GF, TSMC) have two forms of via enclosure: either enclosure (a)
   on ALL sides or (b) enclosure on TWO OPPOSITE SIDES by a larger
   amount and on the other two sides by a smaller amount or zero.  The
   (b) form is really useful for tracked routing, where spacing is
   tight between the long parallel edges of tracks and loose in the
   other direction. Having to leave extra enclosure on two ADJACENT
   sides doesn't seem very useful, unless it's just a weird way of
   requiring half that enclosure on ALL sides, and the foundry
   post-processing moves the via by half the enclosure requirement.
   Was this just the wrong word used in the error message?  Does
   SkyWater130 have OPPOSITE-SIDE-enclosed vias like most commercial
   processes do?

4. The process stack shows NILD4 and NILD4_C with different dielectric
   constants -- what is the difference between these two layers?  Same
   question for NILD3 vs NILD3_C.

5. What is a "ring-shaped mcon"?  This phrase appears several times in
   errors.csv.