the longer term goal is to have everything on the asic (RISC-V controller, DSP cores, LCD controller, etc.) and not have to use an FPGA...but initially I think taping out the analog pieces is the most important part..there are 3 interface scenarios I see: 1. Initial tapeout will probably just be a bunch of components with test fixtures and some analog switching to expose them to the RISC-V 2. All components up to and including ADC/DAC. Depending on the sample rate, high rate SPI, parallel, or SERDES (this would also be available if needing to tap the raw I/Q and skip the RISC-V) 3. All components not including ADC/DAC for an external high speed link. This would just be a single or dual analog pin located so it's easy to create a microstrip line (next to GNDs...probable GND, RX, GND, TX...or GND DUPLEX GND)