Stefan Schippers

10/23/2020, 9:56 PM
also pins Out+ and Out- are declared as output in schematic but as input in symbol; probably not a problem for spice, but its good practice to have matched pin directions (vhdl/verilog will bail out on these mismatches). go into symbol, select Out+ and and Out- red squares and change 'dir' attribute. You can change direction of both by selecting both red squares, hitting 'q' and checking checkbox 'preserve unchanged props'. In general when doing netlists for first time, to check ERC errors, bring up 'View-> Show ERC info window' before extracting the netlist.