@User thank you for the explanation, now i got what you meant by 'matching' that is equal (and minimum) n and p-fet dimensions. P-fets are weaker (in terms of drive strength) w.r.t. N-fets but logic trip point is also set at a lower voltage so this partly compensates the extra p-fet delay.Reduced gate loading capacitance (normally 70+% is due to p-gates) is another advantage. In the end one drawback is probably reduced noise margin (trip point is closer to the '0' logic level)? .