@User, i have some scripts to read spice netlists and produce schematics, preserving the original hierarchy/block partitioning. Spice netlist should include port direction as is done (when enabled while exporting) in CDL netlists (for example from from cadence tools), because this information is needed to reconstruct blocks with the proper port direction. A library of standard cells can be defined so the library symbols will be used instead of building all logic gates from scratch (displaying these as boxes with input pins and output pin(s) ). However there are so many syntax differences and quirks that are specific to rtl to layout flows that it is too difficult to have one-import-fits-all. If you have a spice netlist to do some tests i can try that out. Picture below is an example of such imported schematics.