@User Perfect. Do you have a verilog (only the module port declaration is enough) description for the decred_controller and decred_hash_macro? I can easily get the port direction (input/output/inout) and use this information for better import, otherwise i have to do some heuristics (lot of inout pins if i can't figure out from context). In the mean time will set up the import and link to the library cells. Thanks for now!