@User I have added the decred_hash_macro schematic import to the xschem_sky130 repository. I had to do some simple hand editing after the import; in spice netlist buses are alphabetically ordered instead of numerically, so i have reordered the bits of the wrapper schematic. A README explains the steps i have taken. As usually happens, importing such big designs requires some simple manual intervention. This test was instructive to me to verify the correctness of the sky130 standard cell symbols i created some time ago for xschem using a semi-automatic import from verilog. Xschem did not crash handling such unusually big schematics, and this is nice. However for such designs STA tools on sdf+verilog are (i think) the way to go to check timing / clock tree correctness.