@User for single block analog simulation it's true, its a small circuit, pure digital ASIC flows don't use a schematic at all. There are mixed designs (memories are an example) where you have many power domains (different voltages) and lot of analog circuitry (sense amplifiers, voltage pumps, regulators). These designs don't fit into a typical RTL2GDS flow. Some examples below: 1. a read path simulation for a DDR device, 2. a chip level power network simulation (IR drop)