Creating a layout from schematic means that you are using some schematic symbols that have an associated layout view, may be with parameters, these are in some environments called 'pcells'. A schematic with pcells could be exported as a spice netlist and some backend tool could import these pcells in the layout for placement and routing. However i am not familiar with such a flow, i would be more than happy to contribute to it if there is some work ongoing. One example of such cells are digital standard cells, you place these standard cells (logic gates, latches, flops) in the schematic, the layout places these pre-built cells and needs to route them together. However digital-only design flows do not even use a schematic, since you are using a HDL (Hardware Description Language) such as Verilog, and do logic synthesis / Technology mapping to translate the HDL code to a netlist of standard cells. Placement and routing automatic tools then do the remaining part on the layout.