Hi all, I created a small example for simulating t...
# xschem
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Hi all, I created a small example for simulating the ReRAM cell using xyce and xschem. https://github.com/barakhoffer/sky130_xyce_reram I did some small changes to the Verilog-A model to compile it and an option to change the initial state of the device. Here is a screen shot from an xschem example (It also uses some ngspice hacks to load the I-V curve of the PWL simulation 😀