xschem handles parametric cells and hierarchy from time 0 of its development since i believe this is at the heart of vlsi design: circuit reuse needs all of that. the schematic shown in picture is netlisted in all formats with parameter assignments: example for VHDL (although no one will simulate a metal delay line in VHDL, this is just to show how it works).

...

...

begin

x7 : modello_metal3_single

generic map (

L => 2000 ,

W => 0.5

)

port map (

OUT => net1 ,

IN => INX1

);

...

...