@User @User I certainly don't want to discourage you but coming from an ASIC and process development background before I am sceptical on the possibility to compute parasitics accuracte enough from the layer stack for a digital or analog flow. But as I often say, I like to be proven wrong. Problem is that the layer stack is a simplification of reality. It ignores interaction between the different materials and does not give you the real shapes. It is known the resistivity of metal is not uniform over the crosssection, not all processing layers are likely in the stack-up, processing steps typically round sharp corners, etched interconnects may have side wall angles, the interconnect sidewalls will have roughness - both lower and higher frequency, ... Thing is that something like a fringe capacitance is sensitive to all of these details. At imec interconnect development was done by producing lot's of wafers and measuring the resulting capacitances on it. You could find that for example the chemistry used during a cleaning step in the process influences the measured capacitances, etc What I do find feasible is to define a physics based model and then use SkyWater provided measured capacitances to calibrate this model. Just like SPICE models are also physics based but in the end calibrated on measured transistor performance data. Later then maybe an own capacitance measurement test structure could be produced to give your own calibration input data for your model.