#85 Check the verilog for good style and run automated style / lint / formatting checks on it Issue opened by mithro The verilog in this repository has been formatted to follow a consistent style but that style has not been documented anywhere. We should document the style and add automated checks which make sure the style stays consistent. We may want to move to the Verilog style of be that used by LowRISC projects. That way we could use the Verible tool for checking compliance and eventually auto-formatting. We should also check that the automatic generated verilog output is consistent with the approved style too. google/skywater-pdk