#87 Actually run the test bench, record values into output VCD file and render them with wavedrom in documentation Issue opened by mithro The PDK currently has auto-generated "test" benches for all the standard cells and models. See the following examples; • https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/refs/heads/master/cells/a2111o/sky130_fd_sc_hd__a2111o.tb.v • https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd/+/refs/heads/master/cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.tb.v It would be good to take these test benches, run them through the simulator and saved the output to VCD files. Any open source simulator like Verilator or Icarus Verilog could be used for this. Once there are VCD files, these should then be rendered with wavedrom to give nice waveform diagrams in the documentation on ReadTheDocs. This could use be done with one of the wavedrom Sphinx plugins. google/skywater-pdk