#97 Improve the pg_pin definitions in the liberty timing files Issue opened by mithro Currently the pg_pin definitions look like this;

"pg_pin VGND": {
 "pg_type": "primary_ground",
 "voltage_name": "VGND"
 },
 "pg_pin VNB": {
 "pg_type": "primary_ground",
 "voltage_name": "VNB"
 },
 "pg_pin VPB": {
 "pg_type": "primary_power",
 "voltage_name": "VPB"
 },
 "pg_pin VPWR": {
 "pg_type": "primary_power",
 "voltage_name": "VPWR"
 },

From #95 (comment) we see they should look like this;

I agree with @20Mhz. The right solution looks to be properly annotating the connections. Here is a sample of what this might look like:

```

pg_pin (VNB) {

pg_type : nwell;

physical_connection : device_layer;

voltage_name : "VNB";

}

pg_pin (VPB) {

pg_type : pwell;

physical_connection : device_layer;

voltage_name : "VPB";

}

pg_pin (VPWR) {

pg_type : primary_power;

related_bias_pin : "VNB";

voltage_name : "VPWR";

}

pg_pin (VGND) {

pg_type : primary_ground;

related_bias_pin : "VPB";

voltage_name : "VGND";

}

```

These pins should also be defined in the LEF on the nwell / pwell layers, if they aren't already.

google/skywater-pdk