#103 Some corners in sky130_fd_sc_hdll have ccsnoise data but are not marked as a ccsnoise corner Issue opened by mithro

$ python -m skywater_pdk.liberty libraries/sky130_fd_sc_hdll/v0.1.1

Available corners for sky130_fd_sc_hdll:
  - ff_100C_1v65 
  - ff_100C_1v95 
  - ff_n40C_1v56 
  - ff_n40C_1v65 
  - ff_n40C_1v95 
  - ss_100C_1v60 
  - ss_n40C_1v28 
  - ss_n40C_1v44 
  - ss_n40C_1v60 
  - ss_n40C_1v76 
  - tt_025C_1v80

No

ccsnoise

flags listed there but there are clearly

ccsnoise

data in the files;

$ python -m skywater_pdk.liberty libraries/sky130_fd_sc_hdll/v0.1.1 ss_n40C_1v60 --debug
Generating basic liberty timing files for sky130_fd_sc_hdll at ss_n40C_1v60

Starting to write libraries/sky130_fd_sc_hdll/v0.1.1/timing/sky130_fd_sc_hdll__ss_n40C_1v60.lib (basic from basic)
Overwriting comp_attribute voltage_map with [['VPWR', 1.6], ['VGND', 0.0], ['VNB', 0.0], ['VPB', 1.6]] (existing value of {'VGND': 0.0, 'VNB': 0.0} )
library: Removing lu_table_template ccsn_ovrf
library: Removing lu_table_template ccsn_dc
library: Removing lu_table_template ccsn_pnlh
()   33    0 --  define                                   ''                                       [{'attribute_name': 'switching_power_spl ...
()   60    0 --  comp_attribute                           'technology'                             cmos ...
()   89    0 --  delay_model                              ''                                       table_lookup ...
...
['type bus16']  inf  inf --  base_type                                ''                                       array ...
['type bus16']  inf  inf --  bit_from                                 ''                                       15 ...
['type bus16']  inf  inf --  bit_to                                   ''                                       0 ...
['type bus16']  inf  inf --  bit_width                                ''                                       16 ...
['type bus16']  inf  inf --  data_type                                ''                                       bit ...
['type bus16']  inf  inf --  downto                                   ''                                       true ...
a211o_1.pin X.timing[  0]: Removing ccsn_last_stage
a211o_1.pin X.timing[  0]: Removing ccsn_first_stage
a211o_1.pin X.timing[  1]: Removing ccsn_last_stage
a211o_1.pin X.timing[  1]: Removing ccsn_first_stage
a211o_1.pin X.timing[  2]: Removing ccsn_last_stage
a211o_1.pin X.timing[  2]: Removing ccsn_first_stage
a211o_1.pin X.timing[  3]: Removing ccsn_last_stage
a211o_1.pin X.timing[  3]: Removing ccsn_first_stage
a211o_1.pin X.timing[  4]: Removing ccsn_last_stage
a211o_1.pin X.timing[  4]: Removing ccsn_first_stage
a211o_1.pin X.timing[  5]: Removing ccsn_last_stage
a211o_1.pin X.timing[  5]: Removing ccsn_first_stage
a211o_1.pin X.timing[  6]: Removing ccsn_last_stage
a211o_1.pin X.timing[  6]: Removing ccsn_first_stage
a211o_1.pin X.timing[  7]: Removing ccsn_last_stage
a211o_1.pin X.timing[  7]: Removing ccsn_first_stage
['a211o_1']  256    0 --  leakage_power                            ''                                       [{'value': 0.0002557, 'when': '!A1&!A2&! ...
['a211o_1']  inf  inf --  area                                     ''                                       10.0096 ...
['a211o_1']  inf  inf --  cell_footprint                           ''                                       a211o ...
['a211o_1']  inf  inf --  cell_leakage_power                       ''                                       0.0009418214 ...
['a211o_1']  inf  inf --  pg_pin                                   'VGND'                                   {'pg_type': 'primary_ground', 'related_b ...
['a211o_1']  inf  inf --  pg_pin                                   'VNB'                                    {'pg_type': 'pwell', 'voltage_name': 'VN ...
['a211o_1']  inf  inf --  pg_pin                                   'VPB'                                    {'pg_type': 'nwell', 'voltage_name': 'VP ...
['a211o_1']  inf  inf --  pg_pin                                   'VPWR'                                   {'pg_type': 'primary_power', 'related_bi ...
...

google/skywater-pdk