@User: yes it is doable, but 1. you are likely to do custom instantiation of cells from a library of standard cells (or some primitives if you are using FPGA) 2. you need to prevent the synthesis tool to keep those cells (a string a 3 inverters would be replaced by only only) using dont_touch or keep attribute depending of the synthesis tool 3. you need to break the timing loop through some set_false_path (or equivalent command)