Ever wondered what 1st Year Master student can do in area of Analog IP design with zero experience? Very happy to announce the first PLL IP built from scratch using Sky130 PDK's by @User under 8-week VSD Research IP design Internship program Here's the GitHub repository: https://github.com/lakshmi-sathi/avsdpll_1v8 The whole 8-week journey of building this IP is actually a story worth listening to, and may be we will tell that at our felicitation program Bottom line, if anyone is interested to build SoC around PLL (we are also doing it parallely), you are most welcome to join and contribute The good thing about this IP is its completely open-sourced till GDS level, so you can download, simulate and look at its characteristics Future work involves characterizing same IP across all corners and make it a robust one