If anyone is interested. This was done to improve timing of an (Core + SRAM) using 2 main techniques: Let fail and correct approach to hardware (RAZOR / EDAC): https://npfet.com/publication/zhang_irazor_2018/zhang_irazor_2018.pdf https://ieeexplore.ieee.org/abstract/document/7418031 (memory) Canary approach done with RADHARD team @ STMicro: https://ieeexplore.ieee.org/abstract/document/7062970 These techniques are used for PVTA (Process, Voltage, Temperature, Ageing) variations and reliability. Eventually, we could use such circuits in skywater and other open sourced nodes 🙂