24hrs left for RISC-V MYTH workshop registration Registration for pipe-lined RISC-V MYTH workshop closes in 24hrs https://www.vlsisystemdesign.com/riscv-based-myth/ In meantime, take a look at single stage RISC-V core. Here's the curriculum: Workshop Day wise Content : Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain 1. Introduction to RISC-V basic keywords 2. Labwork for RISC-V software toolchain 3. Integer number representation 4. Signed and unsigned arithmetic operations Day 2: Introduction to ABI and basic verification flow 1. Application Binary interface (ABI) 2. Lab work using ABI function calls 3. Basic verification flow using iverilog Day 3: Digital Logic with TL-Verilog and Makerchip 1. Combinational logic in TL-Verilog using Makerchip 2. Sequential and pipelined logic 3. Validity 4. Hierarchy Day 4: Basic RISC-V CPU micro-architecture 1. Microarchitecture and testbench for a simple RISC-V CPU 2. Fetch, decode, and execute logic 3. RISC-V control logic Day 5: Complete Pipelined RISC-V CPU micro-architecture/store 1. Pipelining the CPU 2. Load and store instructions and memory 3. Completing the RISC-V CPU 4. Wrap-up and future opportunities Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.