Hey There, This is a gentle reminder that registrations for Verilog RTL design and synthesis workshop using Sky130 closes in 48hrs. This might be the final run of this workshop. From next month on-wards, we are coming up with 2 more Brand new workshops with more advanced topics. This might be last chance to get hold of verilog design and synthesis workshop basics Registration link is here: https://www.vlsisystemdesign.com/rtl-design-using-verilog-with-sky130-technology/ With our previous cohort in this workshop, VLSI freshers did a very good job, coming up with their own ideas for verilog modelling and synthesis. VSD might be working with some of them very soon. Freshers and experts - both are welcome in this workshop, so there will be massive exchange of ideas, and you get to work with VSD experts for lifetime All the best and happy learning