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# general
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Kunal

06/20/2021, 3:50 AM
RISC-V core designed by one cohort and 10-bit DAC IP designed by second cohort being used in SoC by third cohort - How about that? Started with high intensity 5-day Workshop + 8-weeks hardware design program "GitHub is indeed the new resume" Please join me in congratulating @User and @User from INDIRA GANDHI DELHI TECHNICAL UNIVERSITY FOR WOMEN in realizing SoC with simple RISC-V MYTH core and 10-bit DAC IP using Sky130 technology in "just 8-weeks" - Sounds crazy, right. Why this achievement is special? Because Mansi and Mili are no experienced SoC designers, but M-Tech Students, still studying, but their dedication towards learning and designing SoC idea from scratch in just 8-weeks, is no less than a miracle. Generally, it takes years to understand what a SoC is, and here they have built SoC, simulated, implemented, found short-comings in existing opensource flow and fixing them as we speak is really commendable Thanks Mansi Mohapatra and Mili Anand - You made VSD and whole country proud. If more people like you join in, then next decade will be dedicated for semiconductor IP and SoC design startups in the country Here's there GitHub link (bug fixing still going on): https://github.com/vsdip/rvmyth_avsddac_interface
🙌 9