VSD Free Webinar - Mixed-signal RISC-V based SoC on FPGA - 23rd July, 7pm IST
webinar helps you get started with a basic mixed-signal FPGA flow, which can be extended to any complex SoC.
VSD and RedwoodEDA conducts 5-day RISC-V based MYTH (Microprocessors for You in Thirty Hours) workshop using transaction level Verilog on Makerchip platform. For people who have done this workshop can use this webinar as an extension to the 5th Day, where RISC-V pipe-lined CPU coded in TL-Verilog is now converted to verilog language and is a part of a mixed-signal SoC
If you are from ASIC/Physical design back-ground, this webinar will complement your existing work, and you would really get to know similarities and differences between ASIC and FPGA flow, which one is preferred under what conditions and why is it preferred
This single webinar connects VLSI students, analog designers, FPGA designers and ASIC designers. It is also an attempt to bring everyone on the same platform, and serves as a starting point for design verification
Stay tuned for follow-up series of FPGA webinars and 5-day hands-on high intensity FPGA workshop, which will be built around OpenFPGA framework and Makerchip visualization software, that enables the whole community to learn FPGA fundamentals along with labs, without actually having a physical FPGA board.
1) "FPGA on eSim" by Guest Speaker - Prof. Kannan M Moudgalya, IIT Bombay
2) "chipIgnite Program" by Guest Speaker - Mike Wishart, CEO eFabless
3) "Tapeout World Program" by Guest Speaker - Naveed Sherwani, Chairman, OSFPGA
4) "Mixed-signal RISC-V based SoC on FPGA" by Webinar Instructor - Shivani Shah
2) RVMYTH RISC-V Core
3) Why FPGAs ?
4) TL - Verilog to RTL verilog using Makerchip
5) Functional Simulation using iverilog
6) FPGA - Steps to create project
7) FPGA - Steps to generate IPs
8) FPGA - RTL simulation
9) FPGA - Synthesis
10) FPGA - Implementation and timing analysis
11) FPGA - Bit-stream generation, FPGA programming and ILA
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