Last 12 hrs - DC Synthesis/STA and Openlane PD curriculum using Sky130
Here's the curriculum for Synopsys DC Synthesis/STA workshop (
Registration closes in 12 hours - Link :
https://www.vlsisystemdesign.com/advanced-synthesis-and-sta-with-dc )
Day 1 : Introduction to Logic Synthesis
• Introduction to Design Compiler
• what is Logic Synthesis ,
• What is netlist , libraries ,
• TCL Quick refresher
• What is DC and how to launch DC ,
• What are the inputs needed to load the design in DC ,
• Loading a basic design in DC ,
• Writing out a basic NL and DDC
Day 2: Basics of STA
• Basics of STA ,
• Delays
• Timing Arcs
• Constraining the Design
• What is STA , setup , hold quick recap .
• What are constraints
• Constraining the Reg2Reg , Reg2IO , IO2Reg Paths
• Input transition and OutputLoad and its effects on IO delays.
Day 3: Advanced Constraints
• Clock Skew and Clock Jitter, its modelling in DC
• Writing SDCs [Synopsys Design Constraints]
• Creating Clocks
• Querying Cells
• Specifying IO Delays
• Specifying Clock Waveforms
• Generated Clocks
• Multi Clock Design
• False Paths
Day 4: Optimizations
• Optimizations in Synthesis
• Combinational Logic Optimization
• Boolean Reduction
• Constant Propagation
• Synthesis Directives
• Synopsys full_case
• Synopsys parallel_case
• Sequential Logic Optimization
• Sequential Constant
• Retiming / Pipelining
Day5 : Quality checks
• Checking Netlist Quality and Generating Reports
• Generating Timing Reports
• max_paths
• nworst
• Boundary Optimizations
• check_design
• check_timing
• HFN (High Fanout Nets)
Here's the curriculum for OpenLANE Physical design workshop (
Registration closes in 12 hours - Link :
https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130 )
Day1 – Inception of open-source EDA, OpenLANE and Sky130 PDK
• How to talk to computers
• SoC design and OpenLANE
• Starting RISC-V SoC Reference design
• Get familiar to open-source EDA tools
Day 2 - Understand importance of good floorplan vs bad floorplan and introduction to library cells
• Chip Floor planning considerations
• Library Binding and Placement
• Cell design and characterization flows
• General timing characterization parameters
Day 3 - Design and characterize one library cell using Magic Layout tool and ngspice
• Labs for CMOS inverter ngspice simulations
• Inception of Layout – CMOS fabrication process
• Sky130 Tech File Labs
Day 4 - Pre-layout timing analysis and importance of good clock tree
• Timing modelling using delay tables
• Timing analysis with ideal clocks using openSTA
• Clock tree synthesis TritonCTS and signal integrity
• Timing analysis with real clocks using openSTA
Day 5 - Final steps for RTL2GDS
• Routing and design rule check (DRC)
• PNR interactive flow tutorial
All the best and happy learning