Last 72hours - From sky130 minimum-transistor length to full-chip - all covered here Hi There, So here's a workshop for anyone and everyone - looking to learn VLSI, looking to learn basics, looking to tapeout an IP using sky130 OR looking to tapeout a chip. This workshop, starts from gate channel length and other rules related to sky130, explains how to install each and every tool on your own laptop, automatically exporting a design from circuit to layout tool and do basic LVS/DRC checks Next, it will walk you through understanding GDS format, advanced extraction options in MAGIC, extraction rules and verification by XOR. These will be followed by various lab exercises on device DRC rules like width, spacing, notch, via size, multiple vias, minimum area rule, angle error, latch-up, antenna and density rules Finally we close this workshop with real life design examples and techniques for LVS, like LVS with subcircuits, blackboxes, SPICE low level components, small analog POR block, layout vs verilog for standard cell and digital PLL example. It's amazing how we were able to make the whole workshop process so simple for users with the help of the latest VSD-IAT cloud VLSI lab based ed-tech - All from your home - No need to install tools. You can login to workshop at your convenient time, finish lectures/labs for that day and logout - That's how simple it is Registration closes in 72hours. Here's the link with details https://www.vlsisystemdesign.com/physical-verification-using-sky130/ All the best and happy learning